4 ms·

I'm very curious what CPU it was, and what the bug was.

by i336_ 10y ago

greglindahl 10y ago
Broadcom Sibyte 1250. I had pre-release silicon, and there was a known bug that prefetch would occasionally hang the chip. I wanted to have a little fun goofing around, so I modified crashme to replace prefetches in the randomly generated code with a noop. A few minutes later, I hung the chip. If I identified the right erratum later, it was: if there is a branch in the delay slot of a branch in a delay slot which is mispredicted, the cpu hangs. It was fixed by making this sequence throw an illegal instruction exception. (It was undefined behavior already, I think.)
- i336_ 10y ago
  Interesting. And... the nesting you describe is messing with my head! :) How did the erratum get fixed? Hardware re-re-release? Definitely filed crashme away, sounds like a useful tool. The Sibyte 1250 sounds cute. There's a "650000000 Hz" in https://lists.freebsd.org/pipermail/freebsd-mips/2009-September/000467.html https://lists.freebsd.org/pipermail/freebsd-mips/2009-Septem... although I'm not sure if MIPS from circa 2002 (?) was that fast (completely ignorant; no field knowledge - definitely want to learn more though). I also noted the existence of the BCM91250E via http://www.prnewswire.com/news-releases/broadcom-announces-new-evaluation-platform-for-its- http://www.prnewswire.com/news-releases/broadcom-announces-n... sibytetm-bcm1250-mipsr-processor-to-accelerate-customers-software-and-hardware-development-75841437.html, which was kind of cool. I like how the chip is a supported target for QNX :) Now I'm wondering what you were using it for. Some kind of network device? (I think I saw networking as one of its target markets.) -- As an aside, I'm also very curious what HN notifier you use, if you use one. (I use http://hnreplies.com/ http://hnreplies.com/ myself, but it's sometimes slow. I saw your message after 4 minutes in this case (fast for HN Replies); typing/research + IRL stuff = delay :) )
  - greglindahl 10y ago
    Our company was PathScale, and we were hoping that the Sibyte 1250 would make a great supercomputing chip. Opteron wasn't out yet, Intel was pricing 64-bit Itanium very high, and this dual-core Sibyte thing was projected to have a reasonable clock and it could do 2 64-bit fp mul-adds/cycle. We had Fred Chow and the GPLed SGI Compiler on our side. And the next revision of the chip had these great 10 gig networking features that I thought I could make work well with MPI, the scientific computing message-passing standard. You can guess how it worked out: Sibyte was late, slow, and buggy. Even simple code sequences like hand-paired multiply-adds would start running at 1/2 speed after an interrupt. Our experienced compiler team was unable to get good perf on several SPECcpu benchmarks despite the code looking good. (Fred didn't have much hair left to pull out!) Soon after we raised our A round we pivoted to using Opteron for compute, building an ASIC for a specialized MPI network, and Fred's team did an Opteron backend for the compiler. The descendant of the network is now called Intel Omni-Path, and is on-package for Xeon Phi cpus.
    - i336_ 10y ago
      I see. Always poignant to hear these kinds of stories. I'm curious as to whether interrupt handling was done underneath the multiprocessing layer or whether interrupts were just hammering the pipeline design. (I assume by "an interrupt" you're referring to slowdown within the fraction of a second after a given interrupt occurred, within the context of floods of interrupts interspersed between instructions?) Very cool to hear that Intel snapped up what you eventually managed to ship, FWIW - and that you were able to pivot in the way you did. Also interesting to hear about Opteron use in the field, my experience is only with tracking the consumer sector. Also, the "GPLed SGI compiler" part you mentioned caught my eye and led me to the EKOpath compiler, and particularly its OSS release in 2011: http://web.archive.org/web/20110616135434/http://pathscale.com/ekopath4-open-source-announcement http://web.archive.org/web/20110616135434/http://pathscale.c... After some floating back and forth I found https://www.phoronix.com/forums/forum/software/general-linux-open-source/880291-what-happened-to-pathscale-s-open-source-path64-compiler-suite?p=880485 https://www.phoronix.com/forums/forum/software/general-linux... which a) mirrored my questioning exactly and b) contained a very nice and straightforward answer, so I guess that put closure on that. Really sad that it never really took off though; faster compilers (https://lwn.net/Articles/447541/ https://lwn.net/Articles/447541/ in/from https://lwn.net/Articles/447529/ https://lwn.net/Articles/447529/) are always something I'm looking for :)

I'm very curious what CPU it was, and what the bug was.

by i336_ 10y ago

I'm very curious what CPU it was, and what the bug was.

Broadcom Sibyte 1250. I had pre-release silicon, and there was a known bug that prefetch would occasionally hang the chip. I wanted to have a little fun goofing around, so I modified crashme to replace prefetches in the randomly generated code with a noop. A few minutes later, I hung the chip. If I identified the right erratum later, it was: if there is a branch in the delay slot of a branch in a delay slot which is mispredicted, the cpu hangs. It was fixed by making this sequence throw an illegal instruction exception. (It was undefined behavior already, I think.)

i336_ 10y ago
Interesting. And... the nesting you describe is messing with my head! :) How did the erratum get fixed? Hardware re-re-release? Definitely filed crashme away, sounds like a useful tool. The Sibyte 1250 sounds cute. There's a "650000000 Hz" in https://lists.freebsd.org/pipermail/freebsd-mips/2009-September/000467.html https://lists.freebsd.org/pipermail/freebsd-mips/2009-Septem... although I'm not sure if MIPS from circa 2002 (?) was that fast (completely ignorant; no field knowledge - definitely want to learn more though). I also noted the existence of the BCM91250E via http://www.prnewswire.com/news-releases/broadcom-announces-new-evaluation-platform-for-its- http://www.prnewswire.com/news-releases/broadcom-announces-n... sibytetm-bcm1250-mipsr-processor-to-accelerate-customers-software-and-hardware-development-75841437.html, which was kind of cool. I like how the chip is a supported target for QNX :) Now I'm wondering what you were using it for. Some kind of network device? (I think I saw networking as one of its target markets.) -- As an aside, I'm also very curious what HN notifier you use, if you use one. (I use http://hnreplies.com/ http://hnreplies.com/ myself, but it's sometimes slow. I saw your message after 4 minutes in this case (fast for HN Replies); typing/research + IRL stuff = delay :) )
- greglindahl 10y ago
  Our company was PathScale, and we were hoping that the Sibyte 1250 would make a great supercomputing chip. Opteron wasn't out yet, Intel was pricing 64-bit Itanium very high, and this dual-core Sibyte thing was projected to have a reasonable clock and it could do 2 64-bit fp mul-adds/cycle. We had Fred Chow and the GPLed SGI Compiler on our side. And the next revision of the chip had these great 10 gig networking features that I thought I could make work well with MPI, the scientific computing message-passing standard. You can guess how it worked out: Sibyte was late, slow, and buggy. Even simple code sequences like hand-paired multiply-adds would start running at 1/2 speed after an interrupt. Our experienced compiler team was unable to get good perf on several SPECcpu benchmarks despite the code looking good. (Fred didn't have much hair left to pull out!) Soon after we raised our A round we pivoted to using Opteron for compute, building an ASIC for a specialized MPI network, and Fred's team did an Opteron backend for the compiler. The descendant of the network is now called Intel Omni-Path, and is on-package for Xeon Phi cpus.
  - i336_ 10y ago
    I see. Always poignant to hear these kinds of stories. I'm curious as to whether interrupt handling was done underneath the multiprocessing layer or whether interrupts were just hammering the pipeline design. (I assume by "an interrupt" you're referring to slowdown within the fraction of a second after a given interrupt occurred, within the context of floods of interrupts interspersed between instructions?) Very cool to hear that Intel snapped up what you eventually managed to ship, FWIW - and that you were able to pivot in the way you did. Also interesting to hear about Opteron use in the field, my experience is only with tracking the consumer sector. Also, the "GPLed SGI compiler" part you mentioned caught my eye and led me to the EKOpath compiler, and particularly its OSS release in 2011: http://web.archive.org/web/20110616135434/http://pathscale.com/ekopath4-open-source-announcement http://web.archive.org/web/20110616135434/http://pathscale.c... After some floating back and forth I found https://www.phoronix.com/forums/forum/software/general-linux-open-source/880291-what-happened-to-pathscale-s-open-source-path64-compiler-suite?p=880485 https://www.phoronix.com/forums/forum/software/general-linux... which a) mirrored my questioning exactly and b) contained a very nice and straightforward answer, so I guess that put closure on that. Really sad that it never really took off though; faster compilers (https://lwn.net/Articles/447541/ https://lwn.net/Articles/447541/ in/from https://lwn.net/Articles/447529/ https://lwn.net/Articles/447529/) are always something I'm looking for :)