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>>> Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Learning? Whoever has worked with FPGA knows that they are completely different to program than CP
by user5994461 10y ago
>>> Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Learning?
Whoever has worked with FPGA knows that they are completely different to program than CPU/GPU.
They are not competing at all. You can't take some computer developers and have them work with FPGA. That'd be like taking a dude who knows XML and put him on optimizing C++ low level algorithms.
For starters, a FPGA doesn't run programs, it describes hardware components.
- rebootthesystem 10y agoI think you are taking the question too literally. Hardware engineers can design FPGA-based hardware optimized for ML. A second set of engineers then uses these boards/FPGA's just as they would GPU's. They write code in whatever language to use them as ML co-processors. This second group doesn't have to be composed of hardware engineers. Today someone using a GPU doesn't have to be a hardware engineer who knows how to design a GPU. Same thing.
- tyingq 10y agoTrue, but if the benefit is there, the software folks will find the right people to assist. Bitcoin is a good example. I'm reasonably sure that FPGAs eclipsed GPU there because some "software person" called the right person in. And it certainly was a competition. Similar for the eventual move to ASIC. If there's enough incremental benefit, it will happen.
- snnn 10y agothere are opencl,blas libraries. You don't have to do everything from the beginning.
- bayesian_horse 10y agoThey are in competition, because increasingly, the deep learning models are run by people who are not experts in machine learning: in deployment, self-driving cars and other machinery. And if it is just about bang-for-buck and scale, FPGAs seem to be quite competitive.
- zamalek 10y agoThere is the evolutionary approach taken by Thompson.[1] There were some spectacular results; though each circuit only worked on the exact FPGA that it was trained on - so that particular approach has no practical applications. [1]: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.50.9691&rep=rep1&type=pdf http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.50....
- bayesian_horse 10y agoI don't actually believe this is true. I find that paper fascinating, and I believe today you could just simulate the hardware definition, rather than work straight on the bitstream and evaluate it in hardware. I also believe that today's FPGAs are more robust against these kinds of bugs. Because, even with some HDL code, these defects or cross-talk incidents could result in difficult to debug errors.