3 ms·
I don't think this is true. I'm not an expert on application scale CPUs, but I think they actually have ROMs that control state machines that execute the instru
by vanjoe 10y ago
I don't think this is true. I'm not an expert on application scale CPUs, but I think they actually have ROMs that control state machines that execute the instructions. This is similar to how regular instructions are stored in memory.
- xenadu02 10y agoMy understanding is that there are several forms of microcode updates. Sometimes the microcode can do simple patches like inserting a nop between problematic instruction combinations. This usually doesn't have much (if any) negative performance implications. The instruction decoder (again AFAIK) is fairly programmable. However if there is a more serious flaw in the actual silicon the microcode must rewrite the problem instructions to emulate the correct behavior and that can make it extremely slow - think emulating floating point but not quite as bad.
- therein 10y agoCorrect, look at this page for an example: https://www.bedroomlan.org/projects/mcasm https://www.bedroomlan.org/projects/mcasm // Minimum Microcode file. cond OP:4; cond uaddr:3; signal /MEMIO = ....1; signal MREAD = ...1.; signal MWRITE = ..1..; field REGMOVE = XX___; signal MAR <- PC = 01...; signal IR <- MEM = 10...; start OP=XXXX; // A tiny fetch instruction /MEMIO, MREAD, MAR <- PC; // hold; // Same as MEMIO, MREAD, MAR <- PC hold, -MREAD, IR <- MEM; // Same as MEMIO, MAR <- PC, IR <- MEM // End of file.