3 ms·
This is one of those interesting cases where RISC-V could eat their (and maybe ARM's) lunch on implementations like this. The wide vector instructions (i.e. not
by microcolonel 10y ago
This is one of those interesting cases where RISC-V could eat their (and maybe ARM's) lunch on implementations like this. The wide vector instructions (i.e. not the packed SIMD, but the -V extension) are width-independent, so you could just make the vector machine narrower on the little core, and switch it to low-frequency in-order.
- Symmetry 10y agoARM recently added a similar wide vector instruction called SVE which works similarly. But yes, that way of doing vectors is really cool. EDIT: Come to think of it, this might be something ARM has been adding deliberately partially to be able to use hetrogenous cores.
- pertymcpert 10y agoARM did it first with SVE. The RISC-V vector extension is just a draft while I believe SVE silicon is being developed now for exascale HPC.
- microcolonel 10y agoCray did it first, that's why there's no patent dispute right now.