That text is talking about the CAS latency, not full read/write latency. CAS latency is the latency for reading from an open row. Rows are small enough that the

That text is talking about the CAS latency, not full read/write latency. CAS latency is the latency for reading from an open row. Rows are small enough that the only way you can persistently hit an open row is if you are either reading sequentially, (in which case the CPU prefetch logic makes the memory latency go away completely) or if you work on such a small working set that you actually hit the cache all the time anyway. On DDR3, the full latency of a miss to ram is, in a low-bandwidth scenario: latency of the full cache system, typically expressed as the L3 latency + latency of opening a row (Trcd) + latency for reading from an open row (Tcas) + latency of passing data from memory controller to L1 cache In a situation with some but not anywhere near full load on the memory subsystem: caches + latency of closing a row (Trp) + latency of opening a row (Trcd) + latency of reading from an open row (Tcas) + latency of passing data to L1 and when doing full tilt random access: caches + time remaining waiting out the minimum allowed row active time of the previous memory access (Tras) + latency of closing a row (Trp) + latency of opening a row (Trcd) + latency of reading from an open row (Tcas) + latency of passing data to L1 The total latency is typically between 50 to 150 ns depending on the CPU and RAM in use.