3 ms·

I think the title may be a bit far fetched. They are talking about 60-100 microseconds latency. DDR3 is usually 9 nanoseconds latency.

by comboy 10y ago

Const-me 10y ago
L2 cache is several nanoseconds. DDR is much slower. This page says 100ns: https://gist.github.com/jboner/2841832 https://gist.github.com/jboner/2841832 This one says 60ns: http://stackoverflow.com/q/4087280/126995 http://stackoverflow.com/q/4087280/126995
- comboy 10y ago
  Got these 9ns from the wikipedia [1]. But 60-100ns would still be 3 orders of magnitude faster than this SSD. I think the difference comes from the latency of operation from the CPU point of view vs actual memory/drive latency.In the article they seem to be talking about the drive latency. 1. https://en.wikipedia.org/wiki/DDR3_SDRAM#Latencies https://en.wikipedia.org/wiki/DDR3_SDRAM#Latencies
  - Tuna-Fish 10y ago
    That text is talking about the CAS latency, not full read/write latency. CAS latency is the latency for reading from an open row. Rows are small enough that the only way you can persistently hit an open row is if you are either reading sequentially, (in which case the CPU prefetch logic makes the memory latency go away completely) or if you work on such a small working set that you actually hit the cache all the time anyway. On DDR3, the full latency of a miss to ram is, in a low-bandwidth scenario: latency of the full cache system, typically expressed as the L3 latency + latency of opening a row (Trcd) + latency for reading from an open row (Tcas) + latency of passing data from memory controller to L1 cache In a situation with some but not anywhere near full load on the memory subsystem: caches + latency of closing a row (Trp) + latency of opening a row (Trcd) + latency of reading from an open row (Tcas) + latency of passing data to L1 and when doing full tilt random access: caches + time remaining waiting out the minimum allowed row active time of the previous memory access (Tras) + latency of closing a row (Trp) + latency of opening a row (Trcd) + latency of reading from an open row (Tcas) + latency of passing data to L1 The total latency is typically between 50 to 150 ns depending on the CPU and RAM in use.
xorblurb 10y ago
Or maybe 3x9 if you are doing wild random accesses in big area, or even worse in huge area if your TLB and then caches start to not hold enough and you effectively need to do multiple accesses for each single ones, but you are right: DRAM is faster. However, caching Optane with real DRAM seems a really good idea (or maybe using Optane as swap could be useful too)

I think the title may be a bit far fetched. They are talking about 60-100 microseconds latency. DDR3 is usually 9 nanoseconds latency.

by comboy 10y ago

I think the title may be a bit far fetched. They are talking about 60-100 microseconds latency. DDR3 is usually 9 nanoseconds latency.

Const-me 10y ago

L2 cache is several nanoseconds. DDR is much slower. This page says 100ns: https://gist.github.com/jboner/2841832 https://gist.github.com/jboner/2841832 This one says 60ns: http://stackoverflow.com/q/4087280/126995 http://stackoverflow.com/q/4087280/126995

comboy 10y ago
Got these 9ns from the wikipedia [1]. But 60-100ns would still be 3 orders of magnitude faster than this SSD. I think the difference comes from the latency of operation from the CPU point of view vs actual memory/drive latency.In the article they seem to be talking about the drive latency. 1. https://en.wikipedia.org/wiki/DDR3_SDRAM#Latencies https://en.wikipedia.org/wiki/DDR3_SDRAM#Latencies
- Tuna-Fish 10y ago
  That text is talking about the CAS latency, not full read/write latency. CAS latency is the latency for reading from an open row. Rows are small enough that the only way you can persistently hit an open row is if you are either reading sequentially, (in which case the CPU prefetch logic makes the memory latency go away completely) or if you work on such a small working set that you actually hit the cache all the time anyway. On DDR3, the full latency of a miss to ram is, in a low-bandwidth scenario: latency of the full cache system, typically expressed as the L3 latency + latency of opening a row (Trcd) + latency for reading from an open row (Tcas) + latency of passing data from memory controller to L1 cache In a situation with some but not anywhere near full load on the memory subsystem: caches + latency of closing a row (Trp) + latency of opening a row (Trcd) + latency of reading from an open row (Tcas) + latency of passing data to L1 and when doing full tilt random access: caches + time remaining waiting out the minimum allowed row active time of the previous memory access (Tras) + latency of closing a row (Trp) + latency of opening a row (Trcd) + latency of reading from an open row (Tcas) + latency of passing data to L1 The total latency is typically between 50 to 150 ns depending on the CPU and RAM in use.

xorblurb 10y ago

Or maybe 3x9 if you are doing wild random accesses in big area, or even worse in huge area if your TLB and then caches start to not hold enough and you effectively need to do multiple accesses for each single ones, but you are right: DRAM is faster. However, caching Optane with real DRAM seems a really good idea (or maybe using Optane as swap could be useful too)