ARM has actually a lot more modularity in its opcodes, in particular it has a whole bunch of different addressing modes for its ALU operands (register and regis

ARM has actually a lot more modularity in its opcodes, in particular it has a whole bunch of different addressing modes for its ALU operands (register and register, register and immediate, register shifted by a register, register shifted by an immediate, register rotated by a register, etc...). There's also the "flag set" bit which says if the instruction is supposed to update the CPSR status flags or not. And then there's the conditional execution flags I talked in my previous post. So with all these combinations you can easily end up with hundreds of possible encodings for an "add" mnemonic. And you have similar shenanigans for memory access instructions (load word, load word and increment after, load word and increment before, load word and increment before, load byte and sign extend...) So you'll probably end up using a combination of multiple LUTs and a bit of code to put it all together.