4 ms·
With how big these chips are getting, I wonder if the next iteration will have an HBM last-level cache on chip.
by Coding_Cat 10y ago
With how big these chips are getting, I wonder if the next iteration will have an HBM last-level cache on chip.
- throwawayish 10y ago"IBM did it first" Well not with HBM (which is DRAM), but huge amounts of L3 SRAM on a MCM... POWER5 I believe.
- phkahler 10y agoThat's the old EHP concept. http://wccftech.com/amd-exascale-heterogeneous-processor-ehp-apu-32-zen-cores-hbm2/ http://wccftech.com/amd-exascale-heterogeneous-processor-ehp... I'd like to have that in the old project quantum package: http://wccftech.com/amd-project-quantum-not-dead-zen-cpu-vega-gpu/ http://wccftech.com/amd-project-quantum-not-dead-zen-cpu-veg... That would be a TFLOPS level supercomputer on your desk.
- keth 10y agoHere is the newest PDF about something like that: http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf http://www.computermachines.org/joe/publications/pdfs/hpca20...