I'm taking a computer architecture grad course right now, and coincidentally our first project involved writing a cache simulator. Obviously, the result was muc

I'm taking a computer architecture grad course right now, and coincidentally our first project involved writing a cache simulator. Obviously, the result was much more coarse-grained than this work. For our project, we only needed to simulate cache accesses and not the content. We also kept track of the LRU block, simulated sub-blocking, and added a FIFO victim cache to the simulation. It was a fun exercise, and I got to learn a bit more C++ in the process. The next project involves building a CPU pipeline simulator, which might be more challenging.