4 ms·
I always imagined that this would work by doubling up the hardware, requiring two logic units to agree, if they didn't then computation work would be redone, mu
by reitzensteinm 16y ago
I always imagined that this would work by doubling up the hardware, requiring two logic units to agree, if they didn't then computation work would be redone, much like a branch prediction failing.
This would obviously not help power consumption at all, but freqeuncy could probably be scaled up quite a bit.
It also assumes that if an error happens it's unlikely to repeat in the same way in the second logic unit. But that may not be a reasonable assumption.
- gdickie 16y agoAt the lowest level, you don't need to double-up, you can use an error correcting code. If the memories and registers on a chip use a multiple-error correcting code, then the underlying error rate could be quite high without making any difference in the user-visible error rate. Similarly you could use noisy-network protocols for on-chip wires, so that each signal path doesn't need to be perfect. Again you don't need to double-up. Instead you lose a small percent to overhead, and a delay in order to encode / decode.
- reitzensteinm 16y agoHow would the error correcting code work for something like a floating point multiplication? Correcting errors in storage is simple, but correcting errors in computation seems like a significantly harder problem.