definitely. plenty of literature on this. the problem, however, is how the delays are calculated. FPGAs have a lot more intermediate logic to determine which ga

definitely. plenty of literature on this. the problem, however, is how the delays are calculated. FPGAs have a lot more intermediate logic to determine which gates are connected to what, and that means intermediate delays that you need to account for. not saying it can't be done or even that it's hard. just a different process.