> Where calculation of a and d is executed in parallel. Why then not to try to reason from the assembler/machine code standpoint? The parallel calculation abo

> Where calculation of a and d is executed in parallel. Why then not to try to reason from the assembler/machine code standpoint? The parallel calculation above could be done in different ways: a) the compiler would emit two "scalar" ADD instructions following one another (allocate registers so independent execution is possible). b) the compiler would coalesce both additions b+c and e+f into one vector operation (let's assume data layout makes such optimization useful), and emitted only one "vector" (SIMD) instruction. In the case a) the two scalar instructions would be fetched "sequentially" by the prefetch unit, but executed in parallel, in two separate instances of the adder ==> "super-scalar". In the other case, the vector operation would not be paired with another instruction which is part of the computation above you mentioned. EDIT: corrected typo in operands of the coalesced additions.