Answering with my own take on the subject. > What format would you propose? How is it different to instructions? It would still be instructions, but either by

Answering with my own take on the subject. > What format would you propose? How is it different to instructions? It would still be instructions, but either by reworking what their operands are and introducing a destination (instruction address + operand port). Another option that could maybe work is a second and mirroring instruction stream that contains only the dataflow/dependencies. > What overhead would you save? On the cache coherence protocol level? Current strategy is write-invalidate, I believe. In some heavy-contention situations (e.g. lots of spin-loops on one variable), using a 'write-once' instruction would traffic. Thinking more radically: With an overhaul of the entire virtual-memory system, a write-once instruction becomes potentially very interesting (Jack Dennis had an interesting paper on the subject: http://www.cs.ucy.ac.cy/dfmworkshop/wp-content/uploads/2014/08/DFM2014-9-On-the-Feasibility-of-a-Codelet-Based-Multi-core-Operating-System.pdf http://www.cs.ucy.ac.cy/dfmworkshop/wp-content/uploads/2014/...). > VLIW Only if you mean something like Mill (https://en.wikipedia.org/wiki/Mill_architecture https://en.wikipedia.org/wiki/Mill_architecture), instead of Itanium.