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> to run multiple instructions in parallel. > The most well known example of this is SIMD. SImd == Single Instruction (multiple data). Correct explanation, u
by minipci1321 10y ago
> to run multiple instructions in parallel.
> The most well known example of this is SIMD.
SImd == Single Instruction (multiple data). Correct explanation, unsuitable illustration.
- hvidgaard 10y agoSIMD is an example of super scalar design. It is running multiple instructions in parallel, they all just happen to be the same instruction. I could have said MIMD, but that is not a term that is well known.
- gpderetta 10y agoI wouldn't call SIMD superscalar. The complexity of a superscalar design is being able to track multiple instructions, their dependencies and their out of order completion [1]. Classical SIMD machines run every lane in lock step. [1] not OoO issue, that would be a proper Out Of Order CPU.
- hvidgaard 10y agoIt's a classical example of how much definition matters. Though, if we define superscalar to mean the instructions can run independenly (i.e. not in lockstep), then I agree that a single SIMD unit is not superscalar. But a design with 2 SIMD units that operate on 2 different data steams independently would be be a superscalar design.
- gpderetta 10y agoI'm no expert, but I think my definition is what historically has been considered superscalar. Yes, the design you described is definitely superscalar, but the fact that the two streams are simd is incidental.
- hvidgaard 10y agoI cannot call myself an expert, but I do have some experience in the domain. The classic example of ILP in a superscalar design is: a = b + c d = e + f g = a + d Where calculation of a and d is executed in parallel. Wikipedia is not entirely clear either, but the entire page gives the impression that it should send instructions to multiple execution units in parallel, in which SIMD would be a single execution unit.
- minipci1321 10y ago> Where calculation of a and d is executed in parallel. Why then not to try to reason from the assembler/machine code standpoint? The parallel calculation above could be done in different ways: a) the compiler would emit two "scalar" ADD instructions following one another (allocate registers so independent execution is possible). b) the compiler would coalesce both additions b+c and e+f into one vector operation (let's assume data layout makes such optimization useful), and emitted only one "vector" (SIMD) instruction. In the case a) the two scalar instructions would be fetched "sequentially" by the prefetch unit, but executed in parallel, in two separate instances of the adder ==> "super-scalar". In the other case, the vector operation would not be paired with another instruction which is part of the computation above you mentioned. EDIT: corrected typo in operands of the coalesced additions.