4 ms·
A somewhat related question: Do PCIe switches know the address windows of their children? Meaning that when one child does an access to one of its peers (anoth
by Unklejoe 10y ago
A somewhat related question:
Do PCIe switches know the address windows of their children? Meaning that when one child does an access to one of its peers (another child), the packet is sent directly to the other child rather than all the way up to the root? I'm not too familiar with how PCIe switches get enumerated, but perhaps it gets configured at that time?
Or does it just behave as a regular bus where every device "listens" for accesses to addresses within their BAR regions (implying that every packet gets broadcast to everyone)? However, I suppose that would be more like a hub rather than a switch...I'll do some more reading!
- angry_octet 10y agoThe TLP header has the destination device's address (in the PCIe tree), so switches just switch. The BARs are related to the host memory map, which has no inherent meaning to devices. nVidia GPU direct introduces a virtual memory region that maps device memory, but I'm not sure if they internally have an IOMMU. For transfers to a device on another bus on the same system the remote device can't be addressed, so it has to ping-pong through system memory, but a device in a different node can be addressed. The device could query the root complex (the OS) to find the bus address of the device with a particular host memory address but I don't know if that is a common idiom. (How this works with Multi-Root IO Virtualisation I'm not sure and it gives me a headache.)