4 ms·
And MIPS in general needed a NOP between a write and a read. That was as-designed, however, because of the way its pipelining worked.
by jdcarter 10y ago
And MIPS in general needed a NOP between a write and a read. That was as-designed, however, because of the way its pipelining worked.
- DonHopkins 10y agoSPARC and other classic RISC pipelined architectures require you to put a nop "Bubble" in the pipeline after a branch if you can't use the instruction slot that's always executed right after the branch. https://en.wikipedia.org/wiki/Bubble_(computing) https://en.wikipedia.org/wiki/Bubble_(computing) https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Hazards https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Hazards More under-appreciated classic RISC trivia: The MIPS is bi-endian, and it's referred to as SPIM when driving backwards. For some reason, Sun never got around to making a bi-endian version of SPARC called CRAPS. http://www.verycomputer.com/31_9f8d907832163a94_1.htm http://www.verycomputer.com/31_9f8d907832163a94_1.htm
- userbinator 10y agoThe democoder in me thinks of "that's not a bug, it's a feature" and wonders if, like the branch delay slot, the delayed memory effect was used to squeeze in an extra instruction and save a cycle or two in optimised code. A similar trick can be found in this interesting article: http://www.reenigne.org/blog/8088-pc-speaker-mod-player-how-its-done/ http://www.reenigne.org/blog/8088-pc-speaker-mod-player-how-... This means that the 8088 will execute the unpatched version of the instruction (as it's already in the prefetch queue by the time it's patched).