4 ms·

A small Lisp-Machine in an FPGA

• krylon 10y ago
  Bonus points for "Wahrscheinlich guckt wieder kein Schwein" - that triggered some fond childhood memories. ;-)
• e19293001 10y ago
  The verilog code had been poorly written. For example, it's not common for a combinational circuit to have an input reset. Latches are inferred in some places that can cause unexpected behavior. That's just my observation though. It's cool to see projects like this. Sadly, it appears to be inactive after seeing the project log.
  • pryelluw 10y ago
    Could you link to an example?
    • gluggymug 10y ago
      There's only one example there. http://www.aviduratas.de/lisp/lispmfpga/code.html http://www.aviduratas.de/lisp/lispmfpga/code.html
      • pryelluw 10y ago
        Thank you.
  • zump 10y ago
    What's a really well written OSS Verilog example? Trying to switch from embedded to RTL design here.
• zengid 10y ago
  Another thread with a related subject (and more current projects): https://news.ycombinator.com/item?id=8340283 https://news.ycombinator.com/item?id=8340283