4 ms·
While the clock speed has largely stagnated, the actual work done per cycle, even on just one core, has gone up significantly. Consider: A double-precision fus
by brandmeyer 10y ago
While the clock speed has largely stagnated, the actual work done per cycle, even on just one core, has gone up significantly. Consider: A double-precision fused multiply-add consumes only 4 cycles of result latency today. The number of memory operations (and other instructions) in flight at any given moment has gone up dramatically, the number of execution units has gone up a little bit (so that the maximum instruction-level parallelism is higher), and so on.
Its not the rapid growth of the 90's and early 2000's, but it is still growth.
- rphlx 10y agoI would argue that we pretty much reached peak single-core x86_64 scalar instruction stream concurrency ~6 years ago with Sandy Bridge. SIMD has gotten wider since then (AVX2, etc) and there are occasional new instructions for certain workloads (including FMA as you noted), but general purpose scalar (non-SIMD) workloads have not gotten much of an IPC boost. Actually, to the extent that those workloads have gotten faster, it's been mostly from the return of clock frequency scaling - from low 3GHz to low 4GHz on the desktop SKUs.