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CVC: An Open Source Industrial Strength Verilog Simulator

• analognoise 10y ago
  CVC is a truly industrial strength Verilog simulator, something that the EDA world desperately needs. It WILL do FULLY back-annotated SDF simulations for ASIC and FPGA designs, it is compiled and FAST, and is open source. It is a project that definitely deserves attention.
• krupan 10y ago
  Is this the same CVC as this? http://www.prnewswire.com/news-releases/pragmatic-c-softwares-cvc-verilog-simulator-now-supports-apple-mac-os-x-94268049.html http://www.prnewswire.com/news-releases/pragmatic-c-software... Also, any relation to GPL cver? https://sourceforge.net/projects/gplcver/ https://sourceforge.net/projects/gplcver/
  • analognoise 10y ago
    Yes! Tachyon Design Automation was formerly Pragmatic C Software. It looks like GPL cver is an ancestor to the current CVC; CVC currently supports Verilog 2005.
    • krupan 10y ago
      Any SystemVerilog support at all? For better or worse, at least some SV constructs are leaking into a lot of RTL code.