4 ms·
> typically 4 or 6 bits in and 1 bit out So these are reducers in algo talk? What about mapping more than 1 bit at a time? Chaining?
by mycall 10y ago
> typically 4 or 6 bits in and 1 bit out
So these are reducers in algo talk? What about mapping more than 1 bit at a time? Chaining?
- duskwuff 10y agoRouting networks in FPGAs are complicated, but essentially unrestricted. You can emulate a multi-bit lookup table by hooking up multiple LUTs to the same inputs, and you can emulate a wider lookup table with a tree of lookups and multiplexers.