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This is a great project, but the idea is not as exotic as it may sound. This is more or less how an FPGA works. Edit: Should also add that there were commercia
by bostand 10y ago
This is a great project, but the idea is not as exotic as it may sound. This is more or less how an FPGA works.
Edit: Should also add that there were commercial products built like this in the 80-90's.
- vvanders 10y agoFPGA -> LUT. (yeah I'm being a bit pedantic but FPGAs are pretty monolithic these days and contain stuff like registers, block ram and DSPs).
- duskwuff 10y agoYep! Only difference is that FPGAs use much smaller lookup tables (LUTs) -- typically 4 or 6 bits in and 1 bit out. For comparison, this project's ALU EPROM has 21 bits in and 16 bits out. Also, FPGAs have real registers. This project is sort of faking registers in some places by wiring output to input in some ROMs. (Which is a clever idea, but flaky and eats a lot of space in the ROM.)
- mycall 10y ago> typically 4 or 6 bits in and 1 bit out So these are reducers in algo talk? What about mapping more than 1 bit at a time? Chaining?
- duskwuff 10y agoRouting networks in FPGAs are complicated, but essentially unrestricted. You can emulate a multi-bit lookup table by hooking up multiple LUTs to the same inputs, and you can emulate a wider lookup table with a tree of lookups and multiplexers.
- DigitalJack 10y agoThe lookup table part, sure, many fpgas use that. The clever part of this was turning a ROM into a flip flop.
- bostand 10y agoFpga and co have not always come with registers. Back in the days this was more or less how it was done.
- duskwuff 10y agoAre there any particular counterexamples you have in mind? The first reprogrammable logic device, the Altera EP300 [1], included a register in each macrocell. So did the first FPGA, the Xilinx XC2064 [2]. I'd be very surprised if there were any FPGAs with no registers. [1]: http://www-inst.eecs.berkeley.edu/~cs294-59/fa10/resources/Altera-history/altera_ep300.pdf http://www-inst.eecs.berkeley.edu/~cs294-59/fa10/resources/A... [2]: http://www.applelogic.org/files/XILINXXC2018LCA.pdf http://www.applelogic.org/files/XILINXXC2018LCA.pdf
- dreamcompiler 10y agoYou can always simulate gates with memory. And by adding feedback, you can build memory with gates. Which means you can simulate non-fed-back gates with fed-back gates.
- wallacoloo 10y agoWhat was described with the ROM sounded more like a latch (transparent for one value of clock, opaque for the other). Did the author actually compose these into flipflops? It read to me as if it that wasn't the case, which just makes it even more cool.