Best independent source I can find is http://www.cpushack.com/CPU/cpu4.html#Sec4Part14 http://www.cpushack.com/CPU/cpu4.html#Sec4Part14. I noticed whilst writi

Best independent source I can find is http://www.cpushack.com/CPU/cpu4.html#Sec4Part14 http://www.cpushack.com/CPU/cpu4.html#Sec4Part14. I noticed whilst writing a verilog implementation - seeing the @PC+ relative modes for immediate data made me dig out my PDP-11 reference card. The number of addressing modes has been halved, gaining a bit for register encoding, and the status register is now in the register file (R2), and R3 is used to generate various constants depending on mode. Compare and contrast: * https://en.wikipedia.org/wiki/PDP-11_architecture#CPU_registers https://en.wikipedia.org/wiki/PDP-11_architecture#CPU_regist... * https://en.wikipedia.org/wiki/TI_MSP430#MSP430_CPU https://en.wikipedia.org/wiki/TI_MSP430#MSP430_CPU