VHDL can model delays for operations, so that any events which they trigger are not triggered until after a delay. This is useful for modeling things like logic

VHDL can model delays for operations, so that any events which they trigger are not triggered until after a delay. This is useful for modeling things like logic gates, which have a propagation delay associated with them. If you're using VHDL for design automation, and you're going to synthesize it to hardware, then the synthesis program does logic mapping to whatever technology (standard cells, FPGA blocks, etc.) is being used, figures out the logic and interconnect delays, and tries to satisfy the requirement that everything be ready when the clock ticks, while allowing a reasonable clock frequency. The way that VHDL handles both uses can be a little confusing.