I feel the need to echo metaphor's reply. Even if tools for FPGAs do become better through the years, it doesn't mean they'll become "sw dev friendly". If you

I feel the need to echo metaphor's reply. Even if tools for FPGAs do become better through the years, it doesn't mean they'll become "sw dev friendly". If you do software you should be fluent with data structures, while on the FPGA/hardware side you "speak" metastability control and timing constraints. Just separate fields of interest. When high level synthesis tools arise (such as Xilinx HLx, C -> straight to FPGA implementation) I still feel they are aiming the wrong audience: these tools still require a more-than-average knowledge of the FPGA fabric and implementation to work with, and that may be a good thing, but defies the HLS paradigm at its roots IMHO. Source: humble experience through my job as an FPGA designer