3 ms·
Quite a few people have been working on making VHDL more accessible by generating it all from Python. Tim Ansell gave a talk about it at LCA 2017 (https://www.y
by cyphar 10y ago
Quite a few people have been working on making VHDL more accessible by generating it all from Python. Tim Ansell gave a talk about it at LCA 2017 (https://www.youtube.com/watch?v=MkVX_mh5dOU https://www.youtube.com/watch?v=MkVX_mh5dOU), and it seems pretty cool.
- gluggymug 10y agoNo way to specify different clocks or resets from what I can see. That's a massive limitation to your designs.