While I also use Verilog, I don't understand your plea. VHDL has it's benefits over Verilog, most notably an actual type system (Verilog has none - you'll be re

While I also use Verilog, I don't understand your plea. VHDL has it's benefits over Verilog, most notably an actual type system (Verilog has none - you'll be redefining the same signal bundles over and over and over again). But yes, Verilator is quite nice. I think both Verilog and VHDL are fairly terrible and are unnecessarily stuck at the connecting-wires-together paradigm. I have high hopes for systems like Clash[1]/Chisel[2]/SpinalHDL[3] to gain more widespread usage and finally make higher abstraction levels and metaprogramming standard in the industry. [1] - http://www.clash-lang.org/ http://www.clash-lang.org/ [2] - https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/ [3] - https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL