3 ms·
This is not a good reason not to use VHDL- GHDL is open source and simulates VHDL? Verilator is only useful if you don't need backannotated timing constraints.
by analognoise 10y ago
This is not a good reason not to use VHDL- GHDL is open source and simulates VHDL?
Verilator is only useful if you don't need backannotated timing constraints.