4 ms·

Please don't use VHDL. Use verilog, as a great cycle accurate FOSS simulator/compiler exists for it (Verilator).

by zump 10y ago

pjmlp 10y ago
I rather use Ada like syntax.
EvgeniyZh 10y ago
Any good Verilog/SystemVerilog book you can recommend?
- blackguardx 10y ago
  http://www.doe.carleton.ca/~jknight/97.478/97.478_02F/PetervrlQ.pdf http://www.doe.carleton.ca/~jknight/97.478/97.478_02F/Peterv... I do FPGA design as part of my job. This is the most concise document I've found that covers everything you need to know to get started. Many verilog books just focus on the language. This short pdf focuses on how to use the language to do hardware design, which is what most people actually want to learn.
  - BillBohan 10y ago
    Many thanks for that link. I wrote VHDL for 10 years and sometimes had to interface to Verilog modules. I only know enough Verilog to read it and get a rough idea of what it does, sometimes asking for help from an expert.
analognoise 10y ago
This is not a good reason not to use VHDL- GHDL is open source and simulates VHDL? Verilator is only useful if you don't need backannotated timing constraints.
q3k 10y ago
While I also use Verilog, I don't understand your plea. VHDL has it's benefits over Verilog, most notably an actual type system (Verilog has none - you'll be redefining the same signal bundles over and over and over again). But yes, Verilator is quite nice. I think both Verilog and VHDL are fairly terrible and are unnecessarily stuck at the connecting-wires-together paradigm. I have high hopes for systems like Clash[1]/Chisel[2]/SpinalHDL[3] to gain more widespread usage and finally make higher abstraction levels and metaprogramming standard in the industry. [1] - http://www.clash-lang.org/ http://www.clash-lang.org/ [2] - https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/ [3] - https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL
SoylentYellow 10y ago
Wow, that is some terrible advice. VHDL is just as valid a choice as Verilog. If a FOSS simulator is your requirement, VHDL has ghdl. Also, many companies only allow VHDL. As better advice, it is worth writing something in both languages to get a feel which one you like better. Both have their own advantages and disadvantages (VHDL: Strongly typed, Verilog: Less verbose).
kevin_thibedeau 10y ago
> cycle accurate FOSS simulator And how do you propose simulating asynchronous logic and delays? How do I back annotate synthesized net and cell delays into your one-true-simulator?

Please don't use VHDL. Use verilog, as a great cycle accurate FOSS simulator/compiler exists for it (Verilator).

by zump 10y ago

Please don't use VHDL. Use verilog, as a great cycle accurate FOSS simulator/compiler exists for it (Verilator).

pjmlp 10y ago

I rather use Ada like syntax.

EvgeniyZh 10y ago

Any good Verilog/SystemVerilog book you can recommend?

blackguardx 10y ago
http://www.doe.carleton.ca/~jknight/97.478/97.478_02F/PetervrlQ.pdf http://www.doe.carleton.ca/~jknight/97.478/97.478_02F/Peterv... I do FPGA design as part of my job. This is the most concise document I've found that covers everything you need to know to get started. Many verilog books just focus on the language. This short pdf focuses on how to use the language to do hardware design, which is what most people actually want to learn.
- BillBohan 10y ago
  Many thanks for that link. I wrote VHDL for 10 years and sometimes had to interface to Verilog modules. I only know enough Verilog to read it and get a rough idea of what it does, sometimes asking for help from an expert.

analognoise 10y ago

This is not a good reason not to use VHDL- GHDL is open source and simulates VHDL? Verilator is only useful if you don't need backannotated timing constraints.

q3k 10y ago

While I also use Verilog, I don't understand your plea. VHDL has it's benefits over Verilog, most notably an actual type system (Verilog has none - you'll be redefining the same signal bundles over and over and over again). But yes, Verilator is quite nice. I think both Verilog and VHDL are fairly terrible and are unnecessarily stuck at the connecting-wires-together paradigm. I have high hopes for systems like Clash[1]/Chisel[2]/SpinalHDL[3] to gain more widespread usage and finally make higher abstraction levels and metaprogramming standard in the industry. [1] - http://www.clash-lang.org/ http://www.clash-lang.org/ [2] - https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/ [3] - https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL

SoylentYellow 10y ago

Wow, that is some terrible advice. VHDL is just as valid a choice as Verilog. If a FOSS simulator is your requirement, VHDL has ghdl. Also, many companies only allow VHDL. As better advice, it is worth writing something in both languages to get a feel which one you like better. Both have their own advantages and disadvantages (VHDL: Strongly typed, Verilog: Less verbose).

kevin_thibedeau 10y ago

> cycle accurate FOSS simulator And how do you propose simulating asynchronous logic and delays? How do I back annotate synthesized net and cell delays into your one-true-simulator?