Correct. For more detail: the only mandated "signaling" for a signaling NaN is that it sets the sticky Invalid bit in the floating-point status register (aka I

Correct. For more detail: the only mandated "signaling" for a signaling NaN is that it sets the sticky Invalid bit in the floating-point status register (aka Invalid exception). It is up to the host processor as to whether it is possible to get a signal on changes to the floating-point exception bits. Some CPU's don't have the ability at all.