4 ms·
Quick Side as the two commenters in this thread seem knowledge. I assume xbegin is a memory barrier. But is it a full fence like mfence or lock prefix? I see
by valarauca1 10y ago
Quick Side as the two commenters in this thread seem knowledge.
I assume xbegin is a memory barrier. But is it a full fence like mfence or lock prefix?
I see a lot of benchmarks using TSX for locking, but one of the nicer features of lock compxchg or lock xchg is they carried an implicit mfence this was nice because it forced reads/writes before the instructions to be completed.
I know xbegin/xend do _more_ then an mfence for reads/writes within the RTM region but do they provide fencing for instructions _after_ their execution?
- gpderetta 10y agoNo idea and don't want to dig into Intel docs right now, but I would be surprised if they were full fences as I think xbegin/xend would only require acquire/release semantics. xacquire/xrelease can be used as modifiers to existing lock prefixed RMW instructions which are already full barriers, giving them optimistic locking capabilities.
- valarauca1 10y agoOkay so I asking around on the intel forums. They fences for instruction ordering, and cache load/flush. But not for load/stores. If you load/store from data within an RTM region (after _xend()) you have no atomic protections.