6 ms·

I find the "open the ISA and they will come" attitude very odd. The ISA is the least of your problems. In fact the cpu itself is not really an issue at this po

by bostand 10y ago

I find the "open the ISA and they will come" attitude very odd. The ISA is the least of your problems. In fact the cpu itself is not really an issue at this point. If you look up what linus and others have been complaining about it has almost never been about the cpu itself (which are all pretty open designs these days). What we need right now is open boot, open firmware and most of all, an open gpu that can compete with the state of the art.

nickik 10y ago
Why cant we do all at the same time? There are different people and interest groups who work on these issues. The goal is to have a secure and open hard and software stack, all the way from the CPU to the top. There is clearly interest in a more standardized fully open ISA and that why it exists. There now other interest groups who want to build hardware for it, and others who want to build stuff on top of it. The people who work on open source firmware all suffer from the close source parts and all the unknowns of the software, and even worse they suffer from the multitude of hardware. Getting some consistency into this space with bottom up open standards can only be good.
unwind 10y ago
In the embedded/SoC/microcontroller space, an open modern easily integrated set of cores seems like a very good thing to have to compete with ARM. If your chip is complex enough to need programmability (perhaps even only internally, i.e. a network switch or something), perhaps the choice between using an open core makes your final product cost $10, whereas tacking on licensing fees to third-parties would make it $11. More margin, more profit, etc.
- bostand 10y ago
  If that is your main concern, why not use another foss cpu with better maturity (leon, openrisc, sparc, lm32 and others) or even an open implementation of a commercial cpu?
  - lgeek 10y ago
    > an open implementation of a commercial cpu? At least the x86, x86-64 and ARM ISAs are covered by patents, so you'd need licensing even for an open independent implementation. I imagine this applies to most other commercial ISAs.
  - aseipp 10y ago
    I think the real answer is: time, place, design set. In another time and place, we'd might be using LEON/SPARC. We don't get to choose our time, though. In particular, LEON is just about the only SPARC implementation I'm aware of whenever it's brought up, while RISC-V already has at least 3-or-4 implementations that have gone to fabrication in the past few years. It has toolchain support and stuff, at least. Oracle being the steward of the latest 10yrs of SPARC design probably has not helped, though, especially wrt IP concerns. LEON is still 32-bit only apparently from a quick search? OR1k has realistically never really had support in almost anything, it seems, other than some binutils/Linux forks and an implementation or two. But it also differs architecturally: delay slots, no 2008 IEEE754, no 64-bit address space OR1k availability at the time of beginning. (Does modern SPARC still have delay slots? That's also a major core change, still.) So if you're going to fix those things, you might as well just start from scratch really, it seems. I've literally never even heard of LM32, despite owning a Lattice FPGA on my desk and it having GCC support, apparently. It's a Harvard design though, and there is no 64-bit support in the chip, so those are two major things that would have to be fixed, and you're still on the hook for e.g. fixing the toolchain for this. So, it's still not free. Also while the core is free, does it really have no IP claims by Lattice? Ultimately RISC-V just had the right support, at the right time (the last ~5 years), and has the right set of features that make it a lot more appealing architecturally. It has an open toolchain that will be (finally!) going upstream in major open source compilers (e.g. no official OR1k/LM32 support in LLVM, LM32 in GCC though), multiple implementations that are size-optimized (picorv32) and speed-optimized (Rocket) and can be openly synthesized/developed, 32/64bit support, needed things like modern upcoming SIMD ISA designs, multiple large and small supporters, compatible chips are beginning to roll out, etc. The ISA design IMO (the chained encoding) makes the instruction set fairly simple and straightforward to write tools for. If you look at all of these efforts, RISC-V is simply a juggernaut in comparison to any other. I do think there is hope out there for more open cores to thrive e.g. due to licensing concerns and cost margins, esp in the embedded space. RISC-V does not have to be the "only" alternative or winner. It's just a very good alternative that has a very "wide reaching" design, with modern niceties (64-bit, SIMD, etc). If I had to pick anything else, I'd probably pick the J-core revival of the SuperH CPU. It's somewhat dated, but the patents/IP have all expired, it's a very dense encoding, a proven architecture (20+ years!), has existing toolchain support (upstream Linux/GCC ports), and in theory can be taped out etc. I've been writing some RISC-V code lately and I'd be interested to see the density vs SuperH -- that matters for stuff like writing a Forth. :)
Gracana 10y ago
What CPU would you use with your open GPU? intel with their management engine is out, you can't get an arm MPU without a gazillion other peripherals onboard, nor a MIPS MPU, but maybe you could license the core.. except now you have those licensing fees and issues. OpenSPARC might be a good candidate, but it's an awfully big device to bootstrap the idea with. RISC-V is nice because the community can start with the simpler device profiles and work their way up.
- bostand 10y ago
  The point I am trying to make is that you are trying to solve the wrong problem, just because it happens to be a fun problem. To address your last statement from another angle: this is not the first FOSS cpu, it only happen to be hipp right now. Significant work has gone into the other alternatives which now risk to be forgotten just because they are not SV darlings.
  - BuuQu9hu 10y ago
    The other FOSS CPUs are irrelevant, precisely because they aren't "darlings" and thus have no momentum.
    - bostand 10y ago
      Is momentum same thing as media exposure? Isn't that very dangerous? Wouldn't it make open source much less democratic since the guy with friends in media will always win instead of the guy with the best ideas?
      - andrewflnr 10y ago
        guy with friends in media will always win instead of the guy with the best ideas This is a description of democracy. :P While media exposure and momentum are not perfectly synonymous, it's rare to find one without the other.
      - andrewflnr 10y ago
wyldfire 10y ago
> I find the "open the ISA and they will come" attitude very odd. It's more like "open the ISA and -- oh! they're here!". The RISC-V Foundation is a who's who of computing. > the cpu itself is not really an issue at this point It sounds to me like you're taking the point of view of someone who values openness for openness' sake. For libre, because it's right. But the Foundation members like openness because it's good business. A lot of the members of the RISC-V Foundation play in the newly-emerged-but-dominating mobile computing space. For tablets and smartphones most of the existing vendors have to pay royalties to ARM. The low end makes up a lot of volume and those royalties start to look more significant over time. The server marketplace is an interesting one too. HPC and cloud computing vendors probably like the idea of being able to have a general purpose processor that is "good enough" and special instruction sets that are useful in their domain. Amazon started a cloud FPGA project recently. Clearly this indicates a likely market for specialized computing jobs. > What we need right now is open boot, open firmware and most of all, an open gpu that can compete with the state of the art. For me/my sake, I think I agree: those would be really great for me to have. But there's not many organizations out there to fund that vision.
- bostand 10y ago
  > It sounds to me like you're taking the point of view of someone who values openness for openness' sake. For libre, because it's right. But the Foundation members like openness because it's good business. Not at all, but a lot of people seem to think riscv = fully FOSS future, just because the ISA is in the datasheet.
  - BuuQu9hu 10y ago
    They are completely wrong, there will be proprietary RISC-V chips. The early ones are more open though.

by bostand 10y ago

nickik 10y ago

Why cant we do all at the same time? There are different people and interest groups who work on these issues. The goal is to have a secure and open hard and software stack, all the way from the CPU to the top. There is clearly interest in a more standardized fully open ISA and that why it exists. There now other interest groups who want to build hardware for it, and others who want to build stuff on top of it. The people who work on open source firmware all suffer from the close source parts and all the unknowns of the software, and even worse they suffer from the multitude of hardware. Getting some consistency into this space with bottom up open standards can only be good.

unwind 10y ago

In the embedded/SoC/microcontroller space, an open modern easily integrated set of cores seems like a very good thing to have to compete with ARM. If your chip is complex enough to need programmability (perhaps even only internally, i.e. a network switch or something), perhaps the choice between using an open core makes your final product cost $10, whereas tacking on licensing fees to third-parties would make it $11. More margin, more profit, etc.

bostand 10y ago
If that is your main concern, why not use another foss cpu with better maturity (leon, openrisc, sparc, lm32 and others) or even an open implementation of a commercial cpu?
- lgeek 10y ago
  > an open implementation of a commercial cpu? At least the x86, x86-64 and ARM ISAs are covered by patents, so you'd need licensing even for an open independent implementation. I imagine this applies to most other commercial ISAs.
- aseipp 10y ago
  I think the real answer is: time, place, design set. In another time and place, we'd might be using LEON/SPARC. We don't get to choose our time, though. In particular, LEON is just about the only SPARC implementation I'm aware of whenever it's brought up, while RISC-V already has at least 3-or-4 implementations that have gone to fabrication in the past few years. It has toolchain support and stuff, at least. Oracle being the steward of the latest 10yrs of SPARC design probably has not helped, though, especially wrt IP concerns. LEON is still 32-bit only apparently from a quick search? OR1k has realistically never really had support in almost anything, it seems, other than some binutils/Linux forks and an implementation or two. But it also differs architecturally: delay slots, no 2008 IEEE754, no 64-bit address space OR1k availability at the time of beginning. (Does modern SPARC still have delay slots? That's also a major core change, still.) So if you're going to fix those things, you might as well just start from scratch really, it seems. I've literally never even heard of LM32, despite owning a Lattice FPGA on my desk and it having GCC support, apparently. It's a Harvard design though, and there is no 64-bit support in the chip, so those are two major things that would have to be fixed, and you're still on the hook for e.g. fixing the toolchain for this. So, it's still not free. Also while the core is free, does it really have no IP claims by Lattice? Ultimately RISC-V just had the right support, at the right time (the last ~5 years), and has the right set of features that make it a lot more appealing architecturally. It has an open toolchain that will be (finally!) going upstream in major open source compilers (e.g. no official OR1k/LM32 support in LLVM, LM32 in GCC though), multiple implementations that are size-optimized (picorv32) and speed-optimized (Rocket) and can be openly synthesized/developed, 32/64bit support, needed things like modern upcoming SIMD ISA designs, multiple large and small supporters, compatible chips are beginning to roll out, etc. The ISA design IMO (the chained encoding) makes the instruction set fairly simple and straightforward to write tools for. If you look at all of these efforts, RISC-V is simply a juggernaut in comparison to any other. I do think there is hope out there for more open cores to thrive e.g. due to licensing concerns and cost margins, esp in the embedded space. RISC-V does not have to be the "only" alternative or winner. It's just a very good alternative that has a very "wide reaching" design, with modern niceties (64-bit, SIMD, etc). If I had to pick anything else, I'd probably pick the J-core revival of the SuperH CPU. It's somewhat dated, but the patents/IP have all expired, it's a very dense encoding, a proven architecture (20+ years!), has existing toolchain support (upstream Linux/GCC ports), and in theory can be taped out etc. I've been writing some RISC-V code lately and I'd be interested to see the density vs SuperH -- that matters for stuff like writing a Forth. :)

Gracana 10y ago

What CPU would you use with your open GPU? intel with their management engine is out, you can't get an arm MPU without a gazillion other peripherals onboard, nor a MIPS MPU, but maybe you could license the core.. except now you have those licensing fees and issues. OpenSPARC might be a good candidate, but it's an awfully big device to bootstrap the idea with. RISC-V is nice because the community can start with the simpler device profiles and work their way up.

bostand 10y ago
The point I am trying to make is that you are trying to solve the wrong problem, just because it happens to be a fun problem. To address your last statement from another angle: this is not the first FOSS cpu, it only happen to be hipp right now. Significant work has gone into the other alternatives which now risk to be forgotten just because they are not SV darlings.
- BuuQu9hu 10y ago
  The other FOSS CPUs are irrelevant, precisely because they aren't "darlings" and thus have no momentum.
  - bostand 10y ago
    Is momentum same thing as media exposure? Isn't that very dangerous? Wouldn't it make open source much less democratic since the guy with friends in media will always win instead of the guy with the best ideas?
    - andrewflnr 10y ago
      guy with friends in media will always win instead of the guy with the best ideas This is a description of democracy. :P While media exposure and momentum are not perfectly synonymous, it's rare to find one without the other.
    - andrewflnr 10y ago

wyldfire 10y ago

> I find the "open the ISA and they will come" attitude very odd. It's more like "open the ISA and -- oh! they're here!". The RISC-V Foundation is a who's who of computing. > the cpu itself is not really an issue at this point It sounds to me like you're taking the point of view of someone who values openness for openness' sake. For libre, because it's right. But the Foundation members like openness because it's good business. A lot of the members of the RISC-V Foundation play in the newly-emerged-but-dominating mobile computing space. For tablets and smartphones most of the existing vendors have to pay royalties to ARM. The low end makes up a lot of volume and those royalties start to look more significant over time. The server marketplace is an interesting one too. HPC and cloud computing vendors probably like the idea of being able to have a general purpose processor that is "good enough" and special instruction sets that are useful in their domain. Amazon started a cloud FPGA project recently. Clearly this indicates a likely market for specialized computing jobs. > What we need right now is open boot, open firmware and most of all, an open gpu that can compete with the state of the art. For me/my sake, I think I agree: those would be really great for me to have. But there's not many organizations out there to fund that vision.

bostand 10y ago
> It sounds to me like you're taking the point of view of someone who values openness for openness' sake. For libre, because it's right. But the Foundation members like openness because it's good business. Not at all, but a lot of people seem to think riscv = fully FOSS future, just because the ISA is in the datasheet.
- BuuQu9hu 10y ago
  They are completely wrong, there will be proprietary RISC-V chips. The early ones are more open though.