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The last time I read about TSX it was a story about how Intel pushed a microcode update to disable TSX because it was flawed. Has this been fixed in newer CPUs?
by 0x0 10y ago
The last time I read about TSX it was a story about how Intel pushed a microcode update to disable TSX because it was flawed. Has this been fixed in newer CPUs? Is there a risk of TSX being flawed on CPUs in the wild (for example, if you're missing the latest microcode updates?)
http://www.anandtech.com/show/8376/intel-disables-tsx-instructions-erratum-found-in-haswell-haswelleep-broadwelly http://www.anandtech.com/show/8376/intel-disables-tsx-instru...
- greglindahl 10y agoIf you have a more-recent-than-2014 kernel, BIOS, or stepping, the feature bit ought to be accurate. So sure, there are some systems in the wild that are broken, but probably not that many.
- 0x0 10y agoLet's say you're deploying to a random cloud VM that may or may not have the latest microcode/BIOS. How do you know if TSX is safe to use? Can it be determined in software by looking at CPUID values? (If so, do all TSX-using libraries/compilers insert such checks?) The risk of subtle locking bugs in multi threaded applications due to CPU bugs makes me want to shy away from the entire feature.
- wtallis 10y agoCPUID values would be sufficient. TSX should be correct on Haswell-EX (Xeon E7), Broadwell except for the tablet SoCs (Core M), and all Skaylake, Kaby Lake and newer.
- greglindahl 10y agoNote that most Linux distros put the latest microcode updates into all of their kernels for any supported version. That means that an updated box with an "old" distro is still going to be OK.
- 0x0 10y agoDoes that work under a hypervisor/xen/VM/whatever? Can you apply a microcode update only within a given VM?
- loeg 10y agoTSX was broken on Haswell CPUs. I don't know which specific newer microarchitecture fixes TSX. Microcode updates have disabled TSX on Haswell for a long time.
- bonzini 10y agoHaswell Xeon E7 do not have the bug and they do enable TSC.
- htns 10y agoI wonder what exactly was the bug? As far as I can google it's not been made public. https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf https://www-ssl.intel.com/content/dam/www/public/us/en/docum... (errata for the CPU I have, and I just tested and the TSX instructions aren't disabled on it btw. I probably enabled TSX in BIOS and forgot about it) mentions minor issues with string instructions' interaction with TSX, rdrand having a chance of hanging if called within a transaction, but the bug blamed for the disabling of TSX (HSW136) is just described as "unpredictable system behavior" "under a complex set of internal timing conditions and system events".