4 ms·

Why he is using 32-bit esp/ebp registers in 16-bit environment? There are 16-bit sp/bp registers. And there is 0xFFFF limit on segment descriptors in real mode

by mkup 10y ago

Why he is using 32-bit esp/ebp registers in 16-bit environment? There are 16-bit sp/bp registers. And there is 0xFFFF limit on segment descriptors in real mode anyway.

deleted 10y ago
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geocar 10y ago
> Why he is using 32-bit esp/ebp registers in 16-bit environment? It might be tooling. A 32-bit assembler (like gas) will turn `mov %esp,%ebp` into `89 e5` while `mov %sp,%bp` becomes `66 89 e5` -- the former being correct when actually in 16-bit. > And there is 0xFFFF limit on segment descriptors in real mode anyway. http://wiki.osdev.org/Unreal_Mode http://wiki.osdev.org/Unreal_Mode
- mkup 10y ago
  > A 32-bit assembler (like gas) will turn `mov %esp,%ebp` into `89 e5` while `mov %sp,%bp` becomes `66 89 e5` -- the former being correct when actually in 16-bit. He is using nasm with "bits 16" directive, so 66 prefix will be emitted for "mov ebp,esp". gas with 32-bit target is totally unrelated to this discussion. > http://wiki.osdev.org/Unreal_Mode http://wiki.osdev.org/Unreal_Mode So what? MBR runs in 16-bit real mode.
  - geocar 10y ago
    > He is using nasm with "bits 16" directive So he is! I had to download nasm to check, but that sounds useful.
- acqq 10y ago
  geocar, you're wrong, mkup is right. I've checked a few disassembled https://onlinedisassembler.com/odaweb/z1mMaYSk/0 https://onlinedisassembler.com/odaweb/z1mMaYSk/0 locations of his binary file (which is identical to the binary I can produce with the nasm): :0000001f 6683c402 add $0x2,%esp :00000025 6655 push %ebp :00000027 6689e5 mov %esp,%ebp There's a 66h "Operand-size override" prefix present in the binaries which is not needed in the 16-bit code. The proper instructions would be "push bp" etc.
deleted 10y ago
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joebergeron 10y ago
I've since updated the article and code on Github to reflect this discssion. Thanks HN as always for teaching me something new.

by mkup 10y ago

Why he is using 32-bit esp/ebp registers in 16-bit environment? There are 16-bit sp/bp registers. And there is 0xFFFF limit on segment descriptors in real mode anyway.

deleted 10y ago

[deleted]

geocar 10y ago

> Why he is using 32-bit esp/ebp registers in 16-bit environment? It might be tooling. A 32-bit assembler (like gas) will turn `mov %esp,%ebp` into `89 e5` while `mov %sp,%bp` becomes `66 89 e5` -- the former being correct when actually in 16-bit. > And there is 0xFFFF limit on segment descriptors in real mode anyway. http://wiki.osdev.org/Unreal_Mode http://wiki.osdev.org/Unreal_Mode

mkup 10y ago
> A 32-bit assembler (like gas) will turn `mov %esp,%ebp` into `89 e5` while `mov %sp,%bp` becomes `66 89 e5` -- the former being correct when actually in 16-bit. He is using nasm with "bits 16" directive, so 66 prefix will be emitted for "mov ebp,esp". gas with 32-bit target is totally unrelated to this discussion. > http://wiki.osdev.org/Unreal_Mode http://wiki.osdev.org/Unreal_Mode So what? MBR runs in 16-bit real mode.
- geocar 10y ago
  > He is using nasm with "bits 16" directive So he is! I had to download nasm to check, but that sounds useful.
acqq 10y ago
geocar, you're wrong, mkup is right. I've checked a few disassembled https://onlinedisassembler.com/odaweb/z1mMaYSk/0 https://onlinedisassembler.com/odaweb/z1mMaYSk/0 locations of his binary file (which is identical to the binary I can produce with the nasm): :0000001f 6683c402 add $0x2,%esp :00000025 6655 push %ebp :00000027 6689e5 mov %esp,%ebp There's a 66h "Operand-size override" prefix present in the binaries which is not needed in the 16-bit code. The proper instructions would be "push bp" etc.

deleted 10y ago

[deleted]

joebergeron 10y ago

I've since updated the article and code on Github to reflect this discssion. Thanks HN as always for teaching me something new.