Interesting! Thanks, that would be really helpful! I'll email you today. I was thinking of somehow combining a form of signature computation at each level (lay

Interesting! Thanks, that would be really helpful! I'll email you today. I was thinking of somehow combining a form of signature computation at each level (layout, schematic, RTL) with some low-overhead logic sprinkled throughout the circuit. The issue is mainly how and where to place the logic, but I'm hoping to get some ideas as I read through prior work.