One of my protoges and I have been discussing groups like STM specifically. We're very torn about it given their strengths on verification & tamper-resistance b

One of my protoges and I have been discussing groups like STM specifically. We're very torn about it given their strengths on verification & tamper-resistance but increased odds of subversion. I mean, if tamper-resistant market is just a few players, then it would make sense for every major agency to focus on them more using all available techniques. Many also own a fab on older technology that they might be consolidating on for cost reduction given how price-sensitive their chips are. Extra risk. It's still unknown to us far as those companies go. "then you really can't trust anything any more" Yep. My recommendation was security through diversity and obscurity at least on the hardware end. Plus developing open hardware and safe methods for making it. "Even at 350nm, how do you know that the part you just bought conforms to the spec? " 250nm was the point where we stopped being able to see the components visually in a microscope. The 350nm or higher can be verified visually against an expected image/layout. You'd order a pile then verify a random percentage like other things. I also thought that image recognition tech could be trained to do it for you after enough samples come in from a given fab. At least, capture all the common stuff that should be there showing it to you. Leaves the rest to be inspected manually to see if it's a defect of the process or something malicious. Additionally, I was going to use it as the TCB for superior, modern chips that do heavy lifting on untrusted computation but get mediated by TCB chip. For advanced stuff, there's companies like ChipWorks that tear them down for what's probably a fortune. There's also possibility of using your own eBeam workstation or whatever to print them plus obscuring whose using it. The printing and packaging systems probably cost millions even for 65-90nm. If you can do 65nm, then we're good as my Core Duo 2 was printed on that... not even best one can do... with it lasting 8 years of application bloat still performing well. So, 65nm is where we can stop if we find a way to produce that in a trustworthy way. Note: Verification side works this way as you might keep the CPU or whatever small enough to verify samples from a fab with those workstations that can handle it. Similarly obfuscated, open software, whatever. Seems easier to control & create the chips instead of just verifying them. Last idea was to get money together to do a FPGA architecture, regular and antifuse, on most cutting-edge node possible. Alternatively, raise money by interested parties to buy Achronix that has 1.4GHz (or similar) FPGA's with 1+ million slices, 10Gbps networking, etc. Idea being the FPGA is open, it's sold at cost by nonprofit, it's periodically verified by various parties, open tooling based on eg Qflow targets it, and it turns into whatever design we need. Gotta verify one, big-ass thing that is mostly same, symmetrical shapes all over with a few custom things (eg I/O). My hardware guy partly inspired this by saying go for the most cutting-edge node because PhD's can barely get them to work much less do clever, stealthy subversions on black boxes. Note: Similar plan to boost open hardware by buying eASIC and their single-layer programmability. FPGA idea can be done that way, too, where the masks are verified by various parties and then monitored by them. So, there's some ideas for this. I'm defaulting on 350-700nm option as (a) verifiable by eye, (b) cheapest to make masks for with MOSIS et al, and (c) gotta start somewhere with at least one thing I can trust. Probably make a Forth- or JOP-like processor to keep number of gates down much as possible. Earlier fabs also had fewer components available to print in terms of their categories. Less stuff to train eyes or computer vision on.