3 ms·
SystemC models as well, I assume : both TLM and Cycle Accurate?
by moflome 10y ago
SystemC models as well, I assume : both TLM and Cycle Accurate?
- gluggymug 10y agoSystemC tends to be used in prototyping more so than verification for projects I have seen. Can possibly be used to make the system emulator also I think. My SoC verification projects have been SystemVerilog only so I am not that familiar with SystemC. Although I believe SystemC can be used for verification, my concern would be how well it performs in simulation together with SystemVerilog components. Whenever you mix two different languages it usually runs slower. SystemVerilog is already not fast but you are stuck with it since a lot of IP is in SystemVerilog. Also splitting the verification environment into SystemC and SystemVerilog for different parts would mean the various metrics like coverage from both sides would have to be merged somehow. It would be a challenge to put it lightly I reckon.