4 ms·

Interesting. Could you point me towards an accessible and up-to-date description of this? I've been telling my compiler students that internally modern x86 comm

by mafribe 10y ago

Interesting. Could you point me towards an accessible and up-to-date description of this? I've been telling my compiler students that internally modern x86 commands are translated to RISC. I need to update my course material.

MrBuddyCasino 10y ago
Seconded, first time I've heard of this.
CalChris 10y ago
Sure. I'm on my iPhone right now. But I'll add to this. Back in the 80s everyone called everything RISC. Check the Bulldog compiler book; the VLIW people were calling VLIW a RISC. Odd since Fisher had worked on microgramming but RISC was very much in vogue. Before there was RISC there was micro programming, horizontal wide microprogramming. The VAX 11/780 was microprogrammed. I think what people are saying when they say Haswell is a RISC is it's microprogrammed. With the Pentium III the uop was 118 bits wide. Bandwidth not an issue. Latency always an issue. http://www.tomshardware.com/reviews/intel,264-6.html http://www.tomshardware.com/reviews/intel,264-6.html With Haswell, the scheduler can Macro Fuse a test and conditional branch. I've never been happy with the shape shifting definitions of RISC over the years but that just doesn't fit any definition of RISC I've seen. Lastly RISC started out as a critique of complex ISAs at a time when the VAX ISA was interpreted with microprogramming loops. Not with RISC loops. So I think history has conflated the terms RISC and horizontal microcode and really they're different. Lastly lastly, there is a difference between the interpreter loop approach VAX took and the translate approach Haswell takes. Also Transmeta compiled x86. But this does not a RISC make. All that's really going on is that Haswell is decoding an x86 instruction and caching the decoding step. The uop cache is relatively more recent (2000?) and long after RISC. But it saves decoding power and latency. The micro architecture wasn't that different before the cache was added.
- gpderetta 10y ago
  Great summary. The only commmon constant among all RISCs is pretty much that they separate load/stores from other operations(i.e. no memory operands). By this definition, the only x86 Intel CPU that could vaguely be called RISC is the Pentium4 (i.e. NetBurst), which not only did break break load/stores from the rest of the operations early in the pipeline (i.e. before the trace cache), but also, for optimal performance, it was best programmed avoiding memory operands but using separate load/stores. More recent Intel CPUs (possibly starting with Nehalem?) only break the load/store component and the actual op of complex operations at the execution stages, and keep them together for the rest of the pipeline.
- kc5tja 10y ago
  In what way is RISC (a horizontal encoding designed to be efficient to decode) different from a 118-bit uop (a horizontal encoding of microarchitectural to-dos in subsequent pipeline stages)? If you can explain without adding yet another shape-shifting definition of what RISC is, or without pigeon-holing it, that would be awesome. From my perspective, a uOP and a RISC instruction are absolutely identical in intent, which is the point of RISC to begin with: the intent to be efficient to decode.
  - CalChris 10y ago
    A RISC ISA is an ISA. It's an architectural contract which can be implemented many ways. That 118 bit uop is a microarchitectural implementation detail. It has a pedigree dating not just to the VAX but to 1957, to Wilkes' EDSAC. In what way is this 118 bit uop not microcode? It is not designed for generality. It isn't exposed (other than # of uops in the Intel Optimization Manual or it is Agner Fog). A complex instruction is in fact interpreted just as POLY was on the VAX. It controls a pipeline. It is anything but Reduced. Calling VLIW and x86 uops RISC doesn't make them RISCs.

by mafribe 10y ago

MrBuddyCasino 10y ago

Seconded, first time I've heard of this.

CalChris 10y ago

Sure. I'm on my iPhone right now. But I'll add to this. Back in the 80s everyone called everything RISC. Check the Bulldog compiler book; the VLIW people were calling VLIW a RISC. Odd since Fisher had worked on microgramming but RISC was very much in vogue. Before there was RISC there was micro programming, horizontal wide microprogramming. The VAX 11/780 was microprogrammed. I think what people are saying when they say Haswell is a RISC is it's microprogrammed. With the Pentium III the uop was 118 bits wide. Bandwidth not an issue. Latency always an issue. http://www.tomshardware.com/reviews/intel,264-6.html http://www.tomshardware.com/reviews/intel,264-6.html With Haswell, the scheduler can Macro Fuse a test and conditional branch. I've never been happy with the shape shifting definitions of RISC over the years but that just doesn't fit any definition of RISC I've seen. Lastly RISC started out as a critique of complex ISAs at a time when the VAX ISA was interpreted with microprogramming loops. Not with RISC loops. So I think history has conflated the terms RISC and horizontal microcode and really they're different. Lastly lastly, there is a difference between the interpreter loop approach VAX took and the translate approach Haswell takes. Also Transmeta compiled x86. But this does not a RISC make. All that's really going on is that Haswell is decoding an x86 instruction and caching the decoding step. The uop cache is relatively more recent (2000?) and long after RISC. But it saves decoding power and latency. The micro architecture wasn't that different before the cache was added.

gpderetta 10y ago
Great summary. The only commmon constant among all RISCs is pretty much that they separate load/stores from other operations(i.e. no memory operands). By this definition, the only x86 Intel CPU that could vaguely be called RISC is the Pentium4 (i.e. NetBurst), which not only did break break load/stores from the rest of the operations early in the pipeline (i.e. before the trace cache), but also, for optimal performance, it was best programmed avoiding memory operands but using separate load/stores. More recent Intel CPUs (possibly starting with Nehalem?) only break the load/store component and the actual op of complex operations at the execution stages, and keep them together for the rest of the pipeline.
kc5tja 10y ago
In what way is RISC (a horizontal encoding designed to be efficient to decode) different from a 118-bit uop (a horizontal encoding of microarchitectural to-dos in subsequent pipeline stages)? If you can explain without adding yet another shape-shifting definition of what RISC is, or without pigeon-holing it, that would be awesome. From my perspective, a uOP and a RISC instruction are absolutely identical in intent, which is the point of RISC to begin with: the intent to be efficient to decode.
- CalChris 10y ago
  A RISC ISA is an ISA. It's an architectural contract which can be implemented many ways. That 118 bit uop is a microarchitectural implementation detail. It has a pedigree dating not just to the VAX but to 1957, to Wilkes' EDSAC. In what way is this 118 bit uop not microcode? It is not designed for generality. It isn't exposed (other than # of uops in the Intel Optimization Manual or it is Agner Fog). A complex instruction is in fact interpreted just as POLY was on the VAX. It controls a pipeline. It is anything but Reduced. Calling VLIW and x86 uops RISC doesn't make them RISCs.