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However, if I put my business hat on and am preparing to bid on a project, I find myself without a strong argument for favoring RISC-V instead of ARM or MIPS.
by gluggymug 10y ago
However, if I put my business hat on and am preparing to bid on a project, I find myself without a strong argument for favoring RISC-V instead of ARM or MIPS.
I think I agree with you on that. It is still early days for RISC-V and it would be a big risk to use the core in an SoC now. Every time I take a look at it as an SoC engineer I see a lot of work that needs doing to integrate it.
- Basically you would be using a heap of dev tools that you never touched before.
- The bus is something called TileLink which is their own protocol so all your peripherals have to be compatible or wrappers have to be made.
- Verification IP seems minimal and not SystemVerilog so you'd have to write it all yourself.
- Your SW guys would need a good emulator. Don't know if theirs is any good.
Other posts are going on about features but if I think about how much SoC work would be required I question whether it is cheaper than ARM or MIPS.
- mafribe 10y agoWhat verification tools would you like to see?
- gluggymug 10y agoSystemVerilog UVM models/protocol checkers for the TileLink buses.
- moflome 10y agoSystemC models as well, I assume : both TLM and Cycle Accurate?
- gluggymug 10y agoSystemC tends to be used in prototyping more so than verification for projects I have seen. Can possibly be used to make the system emulator also I think. My SoC verification projects have been SystemVerilog only so I am not that familiar with SystemC. Although I believe SystemC can be used for verification, my concern would be how well it performs in simulation together with SystemVerilog components. Whenever you mix two different languages it usually runs slower. SystemVerilog is already not fast but you are stuck with it since a lot of IP is in SystemVerilog. Also splitting the verification environment into SystemC and SystemVerilog for different parts would mean the various metrics like coverage from both sides would have to be merged somehow. It would be a challenge to put it lightly I reckon.
- petra 10y agoThere are versions based on risc-v (zScale , and something by elkim roa's group) that include APB and AXI bridges . They might be released as open-source.
- gluggymug 10y agoWhat do you mean by "might be"? I thought the point of all this is to have open-source implementations for people to use in their SoCs.
- _chris_ 10y ago- The bus is something called TileLink which is their own protocol so all your peripherals have to be compatible or wrappers have to be made. FYI: TileLink is not a RISC-V thing, it's a Berkeley/SiFive rocket-chip processor thing. And it has an AXI interface on it anyways.
- gluggymug 10y agoSorry I am just basing this off what I can find. I don't see AXI mentioned in the SiFive docs when I skim through.