3 ms·
The main proposition of RISC is that you can get near 1 IPC without caches provided that you have enough fetch bandwith (which still is not significant problem
by dfox 10y ago
The main proposition of RISC is that you can get near 1 IPC without caches provided that you have enough fetch bandwith (which still is not significant problem for deeply embeded harvard designs). Doing >=1 IPC on CISC architecture with variable length unaligned instructions is essentially impossible without I-cache and significant complexity.
The reason why ARM implementations do uop-based decoding partly lies in the fact that while ARM ISA maps well to traditional RISC pipeline, it does not map so well to superscalar pipeline be it with or without OoO.
- CalChris 10y ago> The reason why ARM implementations do uop-based decoding partly lies in the fact that while ARM ISA maps well to traditional RISC pipeline, it does not map so well to superscalar pipeline be it with or without OoO. Do you have a cite on that? I'd like to know what the problem was with ARM's ISA that presented problems for superscalar. If ARM is doing it then that argues against calling uops RISC instructions.
- _chris_ 10y agoI'd like to know what the problem was with ARM's ISA that presented problems for superscalar. Load/store multiple, for starters. Even just load-pair-increment-address is a pain as it requires 3 write ports. https://arxiv.org/pdf/1607.02318.pdf https://arxiv.org/pdf/1607.02318.pdf