Code density used to be a problem at first for RISC, due to a fixed instruction size of 32 bits typically. But most RISC (or VLIW) ISA have solved the problem b

Code density used to be a problem at first for RISC, due to a fixed instruction size of 32 bits typically. But most RISC (or VLIW) ISA have solved the problem by introducing some level of variable size instructions encoding. It's Thumb2 for ARM, but there's the equivalent for MIPS and others. XTensa from the start used mixed 16/24/32 bits instructions IIRC. Now it used to be clunky at first. For example the first generation Thumb required a processor mode switch between 16 bits instructions only and 32 bits only, with a performance penalty in thumb mode. But with Thumb2 there is no mode switch, both kinds can be mixed freely and the compilers are now smart enough that the performance impact is negligible (could be a gain sometimes with reduced I-cache pressure). For deeply embedded designs, where code size probably matters most, such variable encoding is always supported nowadays with good results, and it's a way to differentiate for more exotic ISA like Cortus or Andes for example. In some specific benchmarks I did the lowest code sizes where from such embedded RISC ISAs, better than x86 for example (YMMV, benchmark your code for best results ;). I haven't benchmarked the RISC-V optional compact code support, but I would expect it to be competitive with x86. Code size is no longer an intrinsic difference for CISC vs RISC from what I've seen, although there are variations between implementations. ======== Edit: one precision, there's no Thumb mode in ARMv8 64 bits mode. One can run 32 bits code using Thumb on an ARMv8 processor in 32 bits mode, but to use 64 bits mode means not using variable size instructions (Thumb), at least for now. But I see this as just an implementation specific decision from ARM. The high level message stays: it's possible to have good code density with a RISC ISA, and all deeply embedded RISC ISA have some form of variable instruction size (at least 16 and 32 bits).