Because you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years ...and earlier you wrote However th

Because you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years ...and earlier you wrote However the vast majority of even kernel/embedded programmers rarely touch assembler these days. It is unclear to me why this double-standard is okay: on one hand, that which is really important, like assembler syntax and mnemonics is exposed and yet not considered relevant, but "micro-architectural details" which really don't hurt me as the coder one way or the other should be hidden. I am not sure who the RISC-V designers expect for their audience, nor why this double standard, but in the light of "the 50 year plan", it appears that the designers haven't given it much thought, if any at all. In the end is this: we have a RISC-V processor design which is not human friendly as far as mnemonics go, and with such processors, relying on compilers will be the only practical solution. Who has not learned from the lessons of history is in for another bitter teaching: such attempts have failed miserably in the past. As evidence, I point to PA-RISC and Itanium. If it were but for a better compiler!