3 ms·

If RISC-V is supposed to scale down to the low end, why doesn't it have delay slots? On an implementation with a simple instruction pipeline, delay slots not on

If RISC-V is supposed to scale down to the low end, why doesn't it have delay slots? On an implementation with a simple instruction pipeline, delay slots not only improve performance, they also simplify the hardware.

rwmj 10y ago
Because you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years (yes really -- see discussions on the mailing list). The very very low end PicoRV32 is not pipelined (unsurprisingly). More ordinary low end (eg. Rocket) has the canonical Hennessey-and-Patterson 5 stage pipeline and still doesn't need to expose branch delay slots in the ISA. I should say also that the classical MIPS -- ie. no instruction dependencies -- was another mistake in hindsight.
- Annatar 10y ago
  Because you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years ...and earlier you wrote However the vast majority of even kernel/embedded programmers rarely touch assembler these days. It is unclear to me why this double-standard is okay: on one hand, that which is really important, like assembler syntax and mnemonics is exposed and yet not considered relevant, but "micro-architectural details" which really don't hurt me as the coder one way or the other should be hidden. I am not sure who the RISC-V designers expect for their audience, nor why this double standard, but in the light of "the 50 year plan", it appears that the designers haven't given it much thought, if any at all. In the end is this: we have a RISC-V processor design which is not human friendly as far as mnemonics go, and with such processors, relying on compilers will be the only practical solution. Who has not learned from the lessons of history is in for another bitter teaching: such attempts have failed miserably in the past. As evidence, I point to PA-RISC and Itanium. If it were but for a better compiler!
  - rwmj 10y ago
    Microarchitecture has a technical meaning here - it means the implementation of the chip. The ISA should be separate from the microarchitecture, although very often they are not (common examples being: branch delay slots, register windows, non-interlocking pipeline stages). The microarchitecture is nothing to do with the assembler syntax or instruction set.
    - Annatar 10y ago
      The microarchitecture is nothing to do with the assembler syntax or instruction set. I know that, my point is that this processor design has completely screwed up priorities in terms of features and usage.
- Annatar 10y ago
  I should say also that the classical MIPS -- ie. no instruction dependencies -- was another mistake in hindsight. What do you mean by "no instruction dependencies"?
  - rwmj 10y ago
    I actually meant "without Interlocked Pipeline Stages" which is what the "IPS" originally stood for in MIPS. Again it's a microarchitectural detail which was exposed through the instruction set, and later MIPS abandoned it.

rwmj 10y ago

Because you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years (yes really -- see discussions on the mailing list). The very very low end PicoRV32 is not pipelined (unsurprisingly). More ordinary low end (eg. Rocket) has the canonical Hennessey-and-Patterson 5 stage pipeline and still doesn't need to expose branch delay slots in the ISA. I should say also that the classical MIPS -- ie. no instruction dependencies -- was another mistake in hindsight.

Annatar 10y ago
Because you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years ...and earlier you wrote However the vast majority of even kernel/embedded programmers rarely touch assembler these days. It is unclear to me why this double-standard is okay: on one hand, that which is really important, like assembler syntax and mnemonics is exposed and yet not considered relevant, but "micro-architectural details" which really don't hurt me as the coder one way or the other should be hidden. I am not sure who the RISC-V designers expect for their audience, nor why this double standard, but in the light of "the 50 year plan", it appears that the designers haven't given it much thought, if any at all. In the end is this: we have a RISC-V processor design which is not human friendly as far as mnemonics go, and with such processors, relying on compilers will be the only practical solution. Who has not learned from the lessons of history is in for another bitter teaching: such attempts have failed miserably in the past. As evidence, I point to PA-RISC and Itanium. If it were but for a better compiler!
- rwmj 10y ago
  Microarchitecture has a technical meaning here - it means the implementation of the chip. The ISA should be separate from the microarchitecture, although very often they are not (common examples being: branch delay slots, register windows, non-interlocking pipeline stages). The microarchitecture is nothing to do with the assembler syntax or instruction set.
  - Annatar 10y ago
    The microarchitecture is nothing to do with the assembler syntax or instruction set. I know that, my point is that this processor design has completely screwed up priorities in terms of features and usage.
Annatar 10y ago
I should say also that the classical MIPS -- ie. no instruction dependencies -- was another mistake in hindsight. What do you mean by "no instruction dependencies"?
- rwmj 10y ago
  I actually meant "without Interlocked Pipeline Stages" which is what the "IPS" originally stood for in MIPS. Again it's a microarchitectural detail which was exposed through the instruction set, and later MIPS abandoned it.