My understanding is that the very large number of registers on the SPARC made context switching very slow --- you need to flush up to several hundred registers

My understanding is that the very large number of registers on the SPARC made context switching very slow --- you need to flush up to several hundred registers onto the physical stack and then restore them again later; while at the same time, processors rarely had enough registers to run non-trivial programs without causing overflow traps. So, the extra complexity wasn't really considered worth it, and it was better to devote silicon to other optimisations rather than exposing what is basically a processor implementation detail in the ISA. However, my knowledge is years old. Have these problems been solved?