2 ms·
Yes, it's not meant to be production ready. Still, the padding you added is particular to Intel/AMD CPUs and this article is more about constrained memory/embed
by NotThe1Pct 10y ago
Yes, it's not meant to be production ready. Still, the padding you added is particular to Intel/AMD CPUs and this article is more about constrained memory/embedded.
On Intel you would not care about the missing slot when you have 256GB memory available.
I've added the atomic<> in the github and updated the article as well.
However with atomic<> it adds an mfence instruction which is not really necessary and might add a ton of latency.
- gpderetta 10y agoYou can specify the memory ordering of operations to get the desired fences. For an spsc queue just load aquires and store releases are sufficient and will have no overhead at all on x86. Don't use operator++ to increment ( it will use an expensive lock xadd) just code the explicit load + add + store sequence. It is safe on this specific case.