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This being HN, I'm hoping someone more competent than me in the area of CPU architectures can comment, but as a scientific programmer some of the details lead m

This being HN, I'm hoping someone more competent than me in the area of CPU architectures can comment, but as a scientific programmer some of the details lead me to adopt a very cautious attitude for now, especially given the 95W TDP. Given the architecture, producing a performance-competitive 8C/16T chip at 68% of Intel's TDP (95W vs 140W) seems very dubious. Most of the things they're touting in the slides amount to little more than finally catching up to Intel (SMT, branch prediction (minus the neural network thing), cache bandwidth, etc.). Also, some of the areas where they seem to exceed current Intel architectures may turn out to be a mixed blessing. For instance, I'm not sure if doubling L2 caches (512kb/core vs 256kb in Intel CPUs) is a great idea given bandwidth limitations and associativity effects. We also don't know the amount of vector registers these CPUs will have, which will greatly influence the performance of optimal CPU-bound code. Can anyone with more experience comment on the low level details they've released, particularly the issues per cycle and cache architecture figures?

wmf 10y ago
Real World Tech is more of the place to discuss microarchitecture.
ronnybrendel2 10y ago
Zen will have 2x128bit vector units. That should result in roughly half the FLOPS for the same core count. http://www.anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism/2 http://www.anandtech.com/show/10591/amd-zen-microarchiture-p... (slide 2 on this page)
Tuna-Fish 10y ago
The advantages I see over Intel are: 1. Wider retire (probably only when executing two threads) 2. 32B fetch from icache. 3. Wider issue when executing from uop cache. 4. Larger icache 5. Larger L2 cache helps hit rate. 6. Larger schedulers, leading to larger practical instruction window 7. Split FP/Int pipelines, meaning more execution resources and instruction window in mixed code. Mixed: 6. Very different branch prediction. AMD has used perceptron predictors before, the talk about AI-driven CPU is just better marketing on this. Perceptrons work much better on some loads, worse on others. What has been released about their newest seems to point to some kind of mitigation of the worst cases of their predictors. Could be great, could be a letdown. 7. Narrower FPU and load-store. This obviously hurts on wide AVX loads, but the adoption of wide AVX so far has been terrible. Narrower FPU gets them shorter distances on chip, leading to higher clocks. Disadvantages: 8. Their split integer schedulers can have bubbles caused by their inability to move instructions between lanes after dispatch. Part of their prediction talk seems to be focused on mitigating this, but it's still something that Intel CPUs just don't have to worry about. 9. Less AGUs. On any code without rmw ops, they probably can't maintain full memory throughput. 10. Larger L2 cache probably hurts L2 latency. Current Intel CPUs are in effect designed for 4uop/clock throughput, with both the frontend and the retire limiting them to that over long term. Especially when both threads are running mixed code, this one appears to have a higher peak throughput. How often it can hit that peak is another question -- if I had to make a quess, I'd say that Zen runs highly optimized code better, but the lower latencies of the modern Intel CPU makes them better at worse-optimized code.

wmf 10y ago

Real World Tech is more of the place to discuss microarchitecture.

ronnybrendel2 10y ago

Zen will have 2x128bit vector units. That should result in roughly half the FLOPS for the same core count. http://www.anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism/2 http://www.anandtech.com/show/10591/amd-zen-microarchiture-p... (slide 2 on this page)

Tuna-Fish 10y ago

The advantages I see over Intel are: 1. Wider retire (probably only when executing two threads) 2. 32B fetch from icache. 3. Wider issue when executing from uop cache. 4. Larger icache 5. Larger L2 cache helps hit rate. 6. Larger schedulers, leading to larger practical instruction window 7. Split FP/Int pipelines, meaning more execution resources and instruction window in mixed code. Mixed: 6. Very different branch prediction. AMD has used perceptron predictors before, the talk about AI-driven CPU is just better marketing on this. Perceptrons work much better on some loads, worse on others. What has been released about their newest seems to point to some kind of mitigation of the worst cases of their predictors. Could be great, could be a letdown. 7. Narrower FPU and load-store. This obviously hurts on wide AVX loads, but the adoption of wide AVX so far has been terrible. Narrower FPU gets them shorter distances on chip, leading to higher clocks. Disadvantages: 8. Their split integer schedulers can have bubbles caused by their inability to move instructions between lanes after dispatch. Part of their prediction talk seems to be focused on mitigating this, but it's still something that Intel CPUs just don't have to worry about. 9. Less AGUs. On any code without rmw ops, they probably can't maintain full memory throughput. 10. Larger L2 cache probably hurts L2 latency. Current Intel CPUs are in effect designed for 4uop/clock throughput, with both the frontend and the retire limiting them to that over long term. Especially when both threads are running mixed code, this one appears to have a higher peak throughput. How often it can hit that peak is another question -- if I had to make a quess, I'd say that Zen runs highly optimized code better, but the lower latencies of the modern Intel CPU makes them better at worse-optimized code.