3 ms·

Solves and creates different issues. With FMV you essentially have to build the compile unit with the highest level of microarch support so that the pre-process

by mcbain 10y ago

Solves and creates different issues. With FMV you essentially have to build the compile unit with the highest level of microarch support so that the pre-processor interprets the intrinsics headers and doesn't eliminate intrinsics you might need. (ICC solves this in a differently annoying way - where all the intrinsics are available, even if they are incompatible with the platform you are on.) For some light entertainment, think about what happens with static initializers and compiling for different microarch flavours. If your C++ static init function happens to generate an AVX insn, and you've only got SSE2, welcome to SIGILL before main().

burntsushi 10y ago
Can't you get the same behavior as icc in gcc/clang by just using target specific optimization options at the function level? See for example stage 1 here: https://gcc.gnu.org/wiki/FunctionSpecificOpt https://gcc.gnu.org/wiki/FunctionSpecificOpt (that document appears dated, but do things still work that way?) Afaik, clang/llvm have similar functionality.
- mcbain 10y ago
  That stage1 example is pretty ugly - using __builtin_ia32<x> would work, but they are the only things harder to read than the intrinsics themselves! Plus there are some intrinsics that are just macros, (sets, masks, etc), and you don't get them from the preprocessor just by setting the function target. As an aside, that page really is dated - it is just early proposals afterall - as SSE5 didn't see light of day like that. VPCMOV ended up in AMD's XOP set. ICC also has its auto as well as manual dispatch options: auto: https://software.intel.com/en-us/node/682440 https://software.intel.com/en-us/node/682440 manual: https://software.intel.com/en-us/node/684505 https://software.intel.com/en-us/node/684505 I believe this is the area where Intel had their knuckles rapped for only working on "GenuineIntel" processors, and why there are big disclaimers on everything now. I've not tried using these myself as they aren't portable solutions.

by mcbain 10y ago

burntsushi 10y ago

Can't you get the same behavior as icc in gcc/clang by just using target specific optimization options at the function level? See for example stage 1 here: https://gcc.gnu.org/wiki/FunctionSpecificOpt https://gcc.gnu.org/wiki/FunctionSpecificOpt (that document appears dated, but do things still work that way?) Afaik, clang/llvm have similar functionality.

mcbain 10y ago
That stage1 example is pretty ugly - using __builtin_ia32<x> would work, but they are the only things harder to read than the intrinsics themselves! Plus there are some intrinsics that are just macros, (sets, masks, etc), and you don't get them from the preprocessor just by setting the function target. As an aside, that page really is dated - it is just early proposals afterall - as SSE5 didn't see light of day like that. VPCMOV ended up in AMD's XOP set. ICC also has its auto as well as manual dispatch options: auto: https://software.intel.com/en-us/node/682440 https://software.intel.com/en-us/node/682440 manual: https://software.intel.com/en-us/node/684505 https://software.intel.com/en-us/node/684505 I believe this is the area where Intel had their knuckles rapped for only working on "GenuineIntel" processors, and why there are big disclaimers on everything now. I've not tried using these myself as they aren't portable solutions.