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https://youtu.be/QTYiH1Y5UV0 https://youtu.be/QTYiH1Y5UV0

• tyingq 10y ago
  Perfect, thanks. Slides like this one were exactly the sort of thing I was looking for: http://i.imgur.com/E42obHv.png http://i.imgur.com/E42obHv.png I do understand that's just one specific implementation (RISCV BOOM), but it does give a little clarity on what level of performance that team is targeting. Edit: Regarding the range of microcontroller to fast 64 bit...that's exactly what I'm trying to understand, mapping what's possible to what's actually being worked on. Roughly, when a production ready RISC-V 64 bit implementation might happen, and how it would compare to ARM/Intel. It's somewhat difficult to tell if the first in the "fast 64 bit" would be more comparable to a Raspberry PI in performance, or more comparable to a very low end Intel x86 processor. So, yes, I get that the ISA doesn't dictate that, but the current groups working on RISC-V implementation does...and it's not clear to me who they all are, what their performance target is, and when they might produce something.
  • BuuQu9hu 10y ago
    It really depends on the implementation, the range will be from microcontroller up to fast 64bit chips. There is also talk of 128bit.