3 ms·
RISC-V isn't quite to that stage yet, but: https://www.crowdsupply.com/onchip/open-v https://www.crowdsupply.com/onchip/open-v https://www.crowdsupply.com/sifi
by BuuQu9hu 10y ago
RISC-V isn't quite to that stage yet, but:
https://www.crowdsupply.com/onchip/open-v https://www.crowdsupply.com/onchip/open-v
https://www.crowdsupply.com/sifive/hifive1 https://www.crowdsupply.com/sifive/hifive1
- duskwuff 10y agoNote that the HiFive is a microcontroller-class RISC-V implementation. (Low pin count, 16 KB SRAM, no external memory interface.) This isn't meant to insult it; it's just in a different space from the LowRISC project.