3 ms·
http://arstechnica.com/gadgets/2006/04/core/4/ http://arstechnica.com/gadgets/2006/04/core/4/ has an explanation of how the P6's data buses were only 64 bits wi
by johntb86 10y ago
http://arstechnica.com/gadgets/2006/04/core/4/ http://arstechnica.com/gadgets/2006/04/core/4/ has an explanation of how the P6's data buses were only 64 bits wide.
- em3rgent0rdr 10y agothanks! That's what I was remembering: "The P6 core's internal data buses for floating-point arithmetic and MMX are only 64 bits wide. Thus the data input ports on the SSE execution units could only be 64 bits wide, as well. In order to execute a 128-bit instruction using its 64-bit SSE units, the P6 must first break down that instruction into a pair of 64-bit instructions which can be executed on successive cycles."