3 ms·
I seem to remember Intel first implemented one of the SIMD instructions as two sequential operations operating on half the size of the full SIMD register. Then
by em3rgent0rdr 10y ago
I seem to remember Intel first implemented one of the SIMD instructions as two sequential operations operating on half the size of the full SIMD register. Then later refinement of the chip (maybe after transistor size shrunk) they then could do the entire SIMD operation at once in parallel instead of sequentially. But this was all hided under the ISA, so you wouldn't know unless checking the clock cycles.
- userbinator 10y agoI'm not sure if you're referring to something different or just confused it with the ALUs on the P4 (NetBurst), which were divided into two 16-bit halves and took one more clock cycle (actually a half, because these were effectively "DDR" clocked) to obtain the full result if there was a carry between them. http://www.realworldtech.com/isscc-2001/7/ http://www.realworldtech.com/isscc-2001/7/ https://gmplib.org/~tege/x86-timing.pdf https://gmplib.org/~tege/x86-timing.pdf
- johntb86 10y agohttp://arstechnica.com/gadgets/2006/04/core/4/ http://arstechnica.com/gadgets/2006/04/core/4/ has an explanation of how the P6's data buses were only 64 bits wide.
- em3rgent0rdr 10y agothanks! That's what I was remembering: "The P6 core's internal data buses for floating-point arithmetic and MMX are only 64 bits wide. Thus the data input ports on the SSE execution units could only be 64 bits wide, as well. In order to execute a 128-bit instruction using its 64-bit SSE units, the P6 must first break down that instruction into a pair of 64-bit instructions which can be executed on successive cycles."
- caf 10y agoAccording to Agner the Skylake puts the top-half of the 256-bit AVX execution units to sleep when they're not in use, and during the warm-up period when you first start using them again, 256-bit operations are done by using the bottom 128-bits of the XUs twice. http://www.agner.org/optimize/blog/read.php?i=415 http://www.agner.org/optimize/blog/read.php?i=415
- Narishma 10y agoI believe that's also how 256-bit AVX is implemented on current-gen consoles' AMD SoCs, as two sequential 128-bit ops.
- castratikron 10y agoThat's a common strategy for Intel: get the instruction out the door and let programmers build on top of it, and then in the next revision, make the instruction fast. One benefit of this strategy is that it makes it more difficult for 'other' x86 vendors to maintain binary compatibility if the industry leader is constantly changing what 'binary compatibility' means.